1. Field of the Invention
The present invention is directed to a DRAM cell arrangement, and method for manufacturing same, wherein a storage capacitor is connected between a selection transistor and a bit line.
2. Description of the Prior Art
In DRAM cell arrangements (i.e., memory cell arrangements having dynamic, random access) what are referred to as one-transistor memory cells are almost exclusively utilized. A one-transistor memory cell includes a selection transistor and a storage capacitor. The information is stored in the storage capacitor in the form of an electrical charge that represents a logical quantity, 0 or 1. This information can be read out via a bit line by driving the selection transistor via a word line.
As a rule, a first source/drain region of the selection transistor is connected to the storage capacitor, and a second source/drain region of the selection transistor is connected to the bit line. A gate electrode of the selection transistor is connected to the word line (see, for example, S. M. Sze, Semiconductor Devices, AT&T Bell Laboratories, Murray Hill, N.J. 1985, page 487, Figure 18a).
Since the memory density is increasing from memory generation to memory generation, the required area of the one-transistor memory cell must be reduced from generation to generation. Since a mere reduction of the dimensions of the memory cell has limits placed on it by the minimum structural size F that can be manufactured in the respective technology, this also involves a modification of the memory cell. Up to the 1-MBit generation, both the selection transistor as well as the storage capacitor were formed as planar components. Beginning with the 4-MBit memory generation, a further reduction in area had to occur by a three-dimensional arrangement of selection transistor and storage capacitor.
One possibility places the storage capacitor not planar, but in a trench (see, for example, K. Yamada et al., "A Deep Trenched Capacitor Technology for 4 MBit DRAMs", Proc. Intern. Electronic Devices and Materials IEDM 85, page 702). The production of such a varied storage capacitor, however, is involved. Further, capacitor dielectrics having high dielectric constants cannot be employed since their deposition is only possible onto substantially planar surfaces.
German Letters Patent 195 19 160 C1 proposes a DRAM cell arrangement wherein the storage capacitor is generated over the selection transistor and the bit line is buried in the substrate. Since the storage capacitor is produced at a service of the substrate, capacitor dielectrics having high dielectric constants can be employed. What is disadvantageous about this DRAM cell arrangement is that the bit line is buried in the substrate. First, it is difficult to produce a buried bit line with low electrical resistance. Second, .alpha. -particles that arise in the substrate cause changes of the charge of the bit line, which can lead to a falsification of the information.
U.S. Pat. No. 4,630,088 discloses that the storage capacitor be connected between a first source/drain region of the selection transistor and the bit line. In this way, both bit line as well as the storage capacitor can be formed at a surface of the substrate. Each memory cell includes a projection-like semiconductor structure that is annularly surrounded by a gate electrode. The memory cells are arranged diagonally offset relative to one another with respect to a word line direction. The storage capacitor includes the first source/drain region, a part of a capacitor dielectric deposited surface-wide and a part of the bit line. The first source/drain region, a channel region and a second source/drain region of the selection transistor are arranged above one another in layer-like fashion.
The present invention is based on the problem of specifying a DRAM cell arrangement wherein a storage capacitor is connected between a selection transistor and a bit line and may be manufactured with increased packing density compared to the prior art. Further, a manufacturing method should be specified for such a DRAM cell arrangement.